Integrated circuits (ICs) and other electronic devices often include arrangements of interconnected field effect transistors (FETs), also called metal-oxide-semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. A typical MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain electrodes. A control voltage applied to the gate electrode controls the flow of current through a controllable conductive channel between the source and drain electrodes.
Power and high-voltage transistor devices are designed to be tolerant of the high currents and voltages that are present in power applications such as motion control, air bag deployment, and automotive fuel injector drivers. One type of MOS transistor used in power applications is a laterally diffused metal-oxide-semiconductor (LDMOS) transistor. In an LDMOS device, a drift space is provided between the channel region and the drain region.
LDMOS devices may be designed to operate in a high-side configuration in which all of the device terminals are level shifted with respect to the substrate potential. Devices configured for high-side operation have been applied in power switchers in DC-to-DC converters, which have respective LDMOS devices for the high side and low side. High-side capable devices may be designed to prevent a direct punch-through path from a body region of the LDMOS device to an underlying substrate.
LDMOS devices are often used in applications, such as automotive applications, involving operational voltages greater than 45 Volts. Breakdown resulting from applying such high voltages to the drain is often prevented through a reduced surface field (RESURF) structure in the LDMOS device design. The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions, thereby reducing the electric field near the surface at the drift region and thus raising the off-state breakdown voltage (BVdss) of the device.
Breakdown events may nonetheless occur at an intrinsic location along the on-state current conduction path between the drain and source of an LDMOS device. Such intrinsic breakdown events, for example, ESD stress, often lead to device degradation and even complete failure of the device. One technique for avoiding intrinsic breakdown involves use of a second device in parallel with the LDMOS device to clamp the drain voltage to a level between the expected operating voltage of the LDMOS device and the intrinsic breakdown voltage of the LDMOS device. Clamping is especially effective if it simultaneously diverts current from the intrinsic device. However, the use of a second device undesirably leads to additional fabrication costs.
In some applications, a lateral clamp diode is used in the end termination regions of the transistor. However, the diode does not scale with transistor width, and photo misalignments in its fabrication affect the breakdown voltage. In other applications, a body contact in the termination regions of an LDMOS device has been modified by placing a vertical clamp diode within the contact. However, the cathode of the clamp diode is fabricated using N+ material and, therefore, its breakdown voltage and utility are thus limited. In addition, without adding cost and complexity to the process flow to introduce an N+ region which is not similar to the existing N+ Source/Drain region, little adjustment can be made to the clamp voltage in such a set-up.